DDR3 8-bit Prefetch buffer why are we calling it DDR still?

I don’t understand how a prefetch buffer is figured into the equation-of the measurement of clock speed when everything involving bit count is measured in relation to bit’s passed along in millions of cycles per second.
1 Hz moves one bit

For example: DDR3 uses an 8 bit prefetch buffer which is why it’s able to transfer the same amount of bit’s as (DDR2’s 4-bit prefetch), at half the clock speed: (just confirming)

But wait a sec, if 1 Hz moves one bit of data, and then we add in the fact that DDR memory moves double the amount per clock cycle, than how are these prefetch bit values being figured into the equation that make up the transfer rates? i.e....If data can move at double the rate of every clock, then is the prefetch another internal clock? If x amount of prefetch bits are moving per clock, why is the DDR clock in the memory controller also moving X amounts of bit per cycle? It sounds like two different clocks doing kind of the same thing.
For example, in my DDR2-6400 system: the mem runs at 200Mhz base X2[DDR] = 400 I/O Bus Clock (excluding the duel channel 800 total speed in this example)
can you see the parallels I'm running into?

Reguardles if we are taking about DDR2-4bit, or DDR3s 8-bit prefetch buffers, where, or what part of the memory execution process are these buffers being carried out? I mean how do you calculate that? I understand that for DDR2-6400 we calculate 200x2[dd] for the 400MHz (per single controller), but with DDR3, you have to calculate at X4 now. so then it's not really DDR double data is it?

How is 4 bits, or the later 8-bit prefetch sizes being moved per cycle if the controller is also-still calculating it's own 2X for the double date rate per cycle?

DDR:
DDR2
DDR3:

 

Its still DDR because with each cycle two bits are being transmitted through 2 data eyes, it behaves exactly the same as all other DDR SDRAM, except that it has a 8n prefetch.

DDR3 prefetch summary This article is very good for understanding the basics of memory

 

the 3 is for generation

 

The only name that does make sense is dual channel and tri channel, their not actually dual and tri channels, their just 1 big uber channel. You would assume that dual channel is 2 independent 64bit channels but its just one big 128bit channel, which is kinda weird.

PS3 uses Quad Channel i believe, but it might just be 4 64 bit channels grouped together into one.

 

Not really. Each RAM stick only has a 64-bit data bus. Dual-channel is two of those grouped together. It can't just be one big 128-bit bus because the RAM isn't that wide.

The one that confuses me is GDDR5. That does four transfers per cycle and it still ends up being called DDR.

 

Yeah but it doesn't operate as two channels, just one big one.

Really? Will DDR5 have four transfers per cycle as well? How do you get 4 data eyes in one cycle... that is weird.

 

DDR just has to transfer data on the rising and falling edge of of the clock signal.

it is not quad pumped, it is dual DDR.

 

True, but physically it's two completely separate channels. Hence the term "dual-channel".

I doubt it. GDDR and DDR are actually very different.

I gather that they get four transfers per cycle by using another set of data links. I would have thought that this would be the same as just doubling the data bus width, but apparently not.

 

sorry i am not expert, you probably read through this:
http://www.qimonda.com/static/download/products/Qimonda_GDDR5_whitepaper.pdf

 

Hello everyone.
I'm not sure if my question made sense, I don't know if we're talking about the same thing. This is very difficult to explain because I'm not an engineer.

Here is what I'm talking about. (lets just stick with DDR2 for now, as it's the same concept)

If DDR2 (6400) 800FSB is running at 200MHz core freq, moves 4 bits-prefetch at one time.
This is the math I get: DDR 200MHz x 4-bits = 800 million bits, / 8 for bytes = 100MBs x 2 DDR x 2-Dual Channel = 400. So where does the 800 FSB come from if we factor in the prefetch bits? (which I never did in the past, and my numbers always came out correct).

In the past before I ever read anything about DDR/DDR2/DDR3 prefetch, I never had an issue figuring out DDR names i.e....
[DDR2_6400] was called that because:
200 x 2-DDR = 400 x 2 both memory controllers = 800FSB

but this DDR3 prefetch thing has got my brain spinning the wrong way. Logically it's understandable that 8-bit's vers 4 is going to give you double the data transfer at the same clock speeds, but I'm just getting mixed up as to how the calculations are figured in. It's all simple math, but the logic screws with my head.
If this stuff gets any more crazy, for my next system I'm going to be walking into the store saying, "If you're out of green, give me the red one".

 

Ok, I made this chart to demonstrate what I think is happening internally, and how the bit's should be calculated to derive at the correct module name. I'm not sure if the prefetch works as I'm demonstrating, but it's the only way I've been able to calculate this, and it seems to work for all the DDR3 speeds!


Example: Here

 

Here is a picture taken from the bit-tech article i linked earlier

Click to view full size!Pretty sure that explains everything..

 

I seen that already Auttie, but it didn't totally make sense to me how the 400 FSB comes into the picture.
What are we multiplying by 4, or 2 to arrive at a 400FSB? I see 8 for bits.
Look at the middle picture for example; it shows 100MHz, moving 8 bits. If I take 100 x 8, I come up with 800bits x 64 / 8 bytes = 6400, which is right, but what is the 400 I/O buffer speed referencing?

Also, the prefetch buffer has an (n) next to the number does that have any impact on the measurement?

 

in the middle picture,

INTERNALLY:
8 bits are being transferred at 100Hz,
which is 8 bits x 100MHz = 800MHz. (1)

EXTERNALLY:
1 bit is transferred every rise and every fall(2 bits total) at 400MHz,
which is 2 bits x 400MHz = 800MHz (2)

so internal (1) and external (2) dataspeed match up.

 

Luke explained it perfectly i believe. The n next to the prefetch number is just for algebra's sake, it doesn't hold significance, all prefetch numbers are in bits currently.

Also when comparing DDR2 to DDR3 you have to remember that because of doubling the prefetch, the DRAM core frequency to I/O buffer has doubled also, which is why the 8n prefetch works. So comparing the top DDR2 you have a 200mhz core with a 4n prefetch, and because 2 bits are transferred each cycle it requires you divide the 4n by 2 giving you 2x the core to I/O.
With DDR3 because you have an 8n prefetch and it is still DDR you divide the 8n by 2, giving you a ratio of 4 between core and I/O, which is the middle example of a 100mhz core and 400mhz I/O buffer.

If you want the reason why they can prefetch more, its mostly because of improved signalling from the fly-by-topography, compared to the older T-bratch symmetry which resulted in a lot of electrical noise from a terminating signal, these problems were rectified with fly-by allowing a greater prefetch, also there was a second clock added to stop bad timing.

 

That was an excellent explanation Luke, thank you! I wasn't visualizing it as you just explained, but it makes sense now in the order you explained it.

I think I got mixed up in thinking that the rising and falling were happening somewhere at a later phase from the prefetch, but then after you emphasized internally, it put me back at the right angle. Great job, Thank you, I totally appreciate the help from you, as well as everyone who posted!
Also,
EDIT:
Thanks Autti, I was posting when you posted so I didn't see your post till just now! You guys were great help!

 

To continue this thread, does anyone know what will be implemented in DDR4? I assume a 16n prefetch, but will ECC becomes standard to eliminate soft errors? New fly-by topology that works like the current buffered DDR3 which is more accurate at tighter timings?

 

btw, Sorry, if I my ask you guys just one last thing, this is another similar question that is driving me nuts. I just took a second look back in the bios to see what my system mem multiplier was set at. it's at (2.4 That's a multiplier, ...Not ratio according to the label)

can you explain this: My ram is running at 200MHz internally base speed, DDR, and duel channel, so the memory bus is 800MHz duel channel. And that's actually what it displays, so that looks great.
Being that the system memory multiplier setting in the bios is not a ratio, but an actual multiplier, [Q]what is 2.4 being multiplied into that's giving me the 800?

either way, the BIOS displays the end result, and it's correct, so I'm not questioning that it's right. I just don't get how they got 2.4? I've tried multiplying 2.4 into 200, 400 800, 333, 1333 just to see what that number it's dividing into. apparently 4.2 is correct because my bus is running at 800, as thats displayed when booting, and in Sandra. But what is it a multiplier of? The manual was not help.


btw, Good question Autti, I'd like to know this also!

 

You have DDR2 which is running at 400MHz (DDR800 due to the double data rate) and your BIOS calls this "800MHz". The base clock of the memory is 200MHz but the I/O frequency is 400MHz and that is the frequency that is usually referred to.

So the theoretical bandwidth at 400MHz is 400 x 2 (DDR) x 128 (Dual Channel) / 8 (bits in a byte) = 12800MB/s.

Your CPU is running at 3000MHz which is 9 x FSB which is 333MHz.

So since your BIOS calls the memory speed by its data rate frequency, the memory frequency as stated is 2.4 x 333 = 800MHz. (really is only 1.2; 333 x 1.2 = 400 "real" MHz".)

A good overclock would be 8 x 400 with the memory set to "2.0x" to get you DDR800, or even 9 x 400.

Cheers

 

Thank you cbjaust.

I didn’t realize each controller had its own 64-bit path. This makes sense now. It’s funny how it’s all simple math, but if you don’t understand the architecture, and topology of the system as a whole, the numbers can really mess with your head. It amazes me how these reviewers are able to rip apart the latest technology and totally understand it inside out. Like these guys at Toms hardware for example, they've got to me electrical engineers.

I appreciate the help, Very good explanation!

Autti's, back to you, sorry!