Flip-Flop

Discussion in 'Electronics & Electrics' started by @rt, Mar 3, 2019.

  1. @rt

    @rt Member

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    Flip-Flop.png

    Hi Guys :)
    A couple of questions about this non-volatile flip-flop posted by a member here a couple of years ago perhaps.
    I have tested this, and without the cores, it’s still an ordinary volatile flip-flop.

    Why are the pair of 2N3638A even there?
    I understand they will just pull the base of either 2N3904 low, and being capacitor coupled,
    the 2N3638A inputs will only act on pulses. So what?
    Why wouldn’t you just pull down the 2N3904 bases directly? Even if it has to be done through capacitors to prevent the 2N3904 staying on, and blowing up.

    Secondly,
    It there an obvious way to add a clock input to this?

    Cheers, Brek.
     
  2. OP
    OP
    @rt

    @rt Member

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    I want to say “mtma”, but I might have it mixed up.
    Not sure what that name actually relates to.
     
  3. OP
    OP
    @rt

    @rt Member

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    img_FlipFlop.png

    It works fine non-volatile with just 2 transistors. They are hard to see, up the top near the connector.

    As far as I can tell, a clock input would just be a 2 transistor AND gate in front of one of the inputs.
     
    Last edited: Mar 3, 2019
  4. Technics

    Technics Member

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    It appears to be a J-K flip-flop so the 2N3638A transistors ensure it correctly performs the toggle operation when both the J and K inputs tied together and triggered. Otherwise it would be an S-R type.
     
  5. OP
    OP
    @rt

    @rt Member

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    Yep. I had it down to an SR flip-flop the same night, which is ok for a shift register.
    It also works with opposite dot windings on a single core, so I’m not sure why two were used.

    To produce a clock input, I’ll use two more transistors for an AND gate, which will also
    convert inputs to positive logic.
     
  6. Technics

    Technics Member

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    It sounds like tiny core memory cores were used originally. It might have been a struggle to fit the windings required to create the full select field strength with the design. I'm not sure about that though.

    That seems reasonable. If you were still using switches as inputs you could implement a clock by controlling the currently grounded side of the two switches but that won't do for making a shift register and you'll need to implement the AND on the inputs.
     
    Last edited: Mar 6, 2019
  7. OP
    OP
    @rt

    @rt Member

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    Screen Shot 2019-03-06 at 4.05.29 pm.png It’s supposed to end up a slow 74xx164 replica with data/clock/reset inputs and parallel output.

    If you don’t mind sanity checking me, let me know if any of this is off:
    Now they are SR flip-flops, all of the R inputs can be tied together to reset all 8 bits on a positive edge if another transistor was used.
    One output of each flip-flop should be ignored unless the NOT output was needed to invert input for the next flip-flop.

    Each flip-flop requires it’s own two transistor AND gate, but a saving could use a single transistor (clock signal) to switch the other seven emitters to ground.
    9 transistors instead of 16 for all 8 flip-flops.

    In the same manner the clock signal in this professional schema could set bits with a clock signal if the 8 bit register had parallel input.
     
    Last edited: Mar 6, 2019
  8. Technics

    Technics Member

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    Won't you need 17 transistors with the Q output tied to S and the !Q output tied to R of the next stage?

    The other thing stands out is that your capture will be triggered by the clock level and not an edge. This means the serial input will cascade through all the stages while clock is active and it won't step through one stage at a time on each clock pulse.
     
  9. mtma

    mtma Member

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    The other thing to watch out for is how current hungry the unbuffered core is.

    If, in theory you assembled the circuit in post 7 and tried to use it for whatever, the sum of the C-E junctions of both the open collector input buffer and the open collector clock buffer has to go below about 0.65V to reliably flip the latch core. With the original circuit the internal trigger current peaks at around 50mA with 5V operating voltage. In particular the clock transistor probably needs to be bigger in such an arrangement to ensure you have adequate voltage margin.

    This would have been a similar issue using the same arrangement to clock the original design, but in that case you're dealing with the base to emitter voltage of the emitter follower arrangement.
     
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  10. OP
    OP
    @rt

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    Technics I didn’t see it, but given my cores are large, and should slow the whole thing down, I figure using displacement current through a capacitor should work?
    Similar to the capacitor in series with the switches in the original circuit.
    Though I believe those are probably there to prevent holding the 2N3904 bases down, and heating them up.
     
  11. OP
    OP
    @rt

    @rt Member

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    Only the flip-flops will fit on this board, so there’s room for experimentation on another.

    Zero Ohm links hanging in the air are core windings.
     

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  12. Technics

    Technics Member

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    The speed isn't the issue. The issue is that you need each stage to sample the output from the previous stage before the previous stage changes to the new state and not sample after the change of state. If you were to AC couple the clock with a series cap then it still won't work reliably. A flip flop with a clock that is truly edge triggered would be a reliable option but would require considerably more transistors per stage (usually implemented as a second latch with enable inverted. I.e a master-slave configuration). A compromise might "store" each stages output state in a capacitor while the shift is occurring. Similar to the way a dynamic shift register is implemented but this would only be dynamic while performing the shift. In the un-clocked steady state the latches would hold the output and be non-volatile.
     
  13. OP
    OP
    @rt

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    Maybe I could use a shift register :D to iterate the elements from the carry end through to the input end.
    It is working, so far without a clock, and does just send the input value straight through all bits.

    I could use a row of transistors as a clock to count through that way, and it appears I use the same number of transistors all up,
    as it would have taken to make D flip-flops in the first place.
     

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