Discussion in 'Intel x86 CPUs and chipsets' started by chainbolt, Sep 19, 2007.
45nm Penryn wafer
45nm Nehalem wafer
One Nehalem wafer is enough for me.
=o imagine the money they waste holding it!
It is like enough money to make me a new pc every month for a few years!!
If Penryn is already 20% faster, just by shrinking the transistors and enlarging the cache, Nehalem with a completely new architecture will probably blow away everything in its path:
exciting times now for cpu development! Compared to the slump with the pentium 4 period.
They look to be holding it very carefully around the edges, perhaps they will turn into Engineering samples
come on guys, even if that wafer contains $100K worth of potential chips, its nothing compared to the cost of hosting IDF
Display samples are generally bummed chips, which appear quite often in early rounds of manufacture. I assure you that wafer will not be cut up and sold. It will sit in a display cabinet for the rest of its life or pawned off to a lucky employee. AFAIK the dies need to be protected if they are to be allowed to come into contact with an 'unclean' environment, otherwise small particles of dust and fingerprints would quickly cause problems.
They hold it around the edges because fingerprints are just plain unsightly .
Exciting stuff to come for sure.
very interesting indeed??
someone on OCAU needs to invent a time machine...
i want new cpus now!!
does anyone know how they actually turn thse into chips? Are they cut into smaller squares?
What about the ones on the edges that look like only half a chip?
Funny, just the same question crossed my mind. The real reason by AMD/Intel are so keen to shrink the dies is that it allows them to "burn" more of them on one wafer, which is grealty reducing cost. It is said that Intel gained a 30% cost advantage over AMD because they were 1 year ahead with 65nm, and now obviously again 1 year ahead with 45nm.
The wafer size used for the current 65nmm process (used by Intel for mass production since mid 2005) is 300mm. Before they used 200mm wafer. So, it's not only reducing the die size but also increasing the wafer size. Intel spent 3 billion USD (!) for their first 300mm wafer fab that produced 65nm dies, existing production facilties cannot simply changed.
How Many Squares (die) Fit in a Circle (wafer)? Fab Revenue Simulation and Optimization.
So these 'wafers' are actually circular objects? So that's a whole bunch of dies that form a wafer?
exaclty: the wafer is a circular piece of silicon, on which the dies are burnt by a "lithography" process
More explained in my OCAU article here:
So the transistors are actually 'burnt' into the silicon with light? As in, its not a physical transistor... but a 'path' that is burnt into the material?
And then, these wafers are diced up and made into the actual chip?
Any reason why they are round? I would have thought you'd fit more on a square....
yes, with light The die itself is silicon burn by a beam of light I was also surprised when I learned this.
yes, capacitors added, IHS, andwhatever it takes
No idea, a square would certainly yield more dies. But obviously there must be reason.
Hmm... seems like AMD were right all along then... IMC, HyperTransport.
When will Intel ever come up with their own ideas? Except for adding more cache.
I am not interested in ideas, but performance. And Intel stuff is currently performing better.
Hehe actually Intel were first when it was called "Netburst" iirc