I recently assembled a dual processor Tualatin-on-BX system. I expected to use Slot-T adapters, but was forced to modify Coppermine slotkets when I found the Slot-Ts do not support SMP on my board. After reading Intel's Universal S370 Design Guide (aka how to design a motherboard to support both Coppermine and Tualatin socket 370 processors), I was uncomfortable with the slotket modification - It circumvents the protection Intel implemented to prevent the Tualatin's AGTL (1.25v) pins from receiving Coppermine AGTL+ (1.5v) signals, but does nothing to address the overvoltage. The design guide states this will result in 'eventual processor failure'. I decided to investigate the possibility of modifying the Coppermine slotkets to fix the problem. The Slot-T, and most good quality slotkets, use TI's SN74TVC16222a 22-bit voltage clamp to protect the processor's low voltage i/o components. This device prevents signal voltages from exceeding the reference voltage, Vref, presented to it's reference transistor. I was therefore looking for a way to change the reference voltage from 1.5v to 1.25v - so I got out the DMM and loupe to see how the Slot-T derives it's reference voltage. I was surprised to find it doesn't - the Slot-T Vref is 1.5v, same as on a Coppermine slotket. IOW, the Slot-T is nothing more than a factory-modified Coppermine slotket and does not translate signals to Tualatin specifications.
same thing is true for the Powerleap adaptor. They all run Tualatins with Vtt of 1.5V. Anyway, I've been running Tualatins in BX boards for over a year now, and they are still doing well. edit: I meant Vtt. Vref is specified as 2/3 of Vtt.
Re: Re: Slot-T vs. modded Slotket Thanks for posting - I was wondering about the Powerleap, and it's nice to know my processors are unlikely to fail in the short term. I run my systems 7x24 - does yours have a years worth of hours? I was considering using resistor dividers to set the voltage clamp reference to 1.25v, and the AGTL reference to 2/3 of that, but I'm beginning to think the risk is low and not worth the trouble - my time might be better spent trying to get the system stable at 150Mhz FSB. It works great at 140 with all memory timings maxed out, but I get a few memtest errors at 150 and backing off the memory speed just makes it worse! Kinda counterintuitive
p2b, i believe the slot T does translate the Tualatin AGTL bus thru the 16222a to at least represent the AGTL+ bus!!! i thought that was the most important difference between the Tualatin & the FCPGA CPU's, apart from the pin specs. i'm running a Slot T on an Abit BE6-2, BX board, & it's great at stock speeds...haven't even tried o'clocking yet. i have a few slot adaptors, including the adaptors that have the 16222a chip yet i chose to use the slot T adaptor, because of slimplicity and possibility of damage to the system, even though i'm trained in micro minature soldering. I'm surprised that the Slot T doesn't support SMP, i thought it did???? I've no problem with the Tualatin on my system with the Slot T..It's very quick for a system that was not designed for the CPU. I guess it's a bonus for those who thought it never could?? I guess if you are querying the longevity that much, then you would be looking for differing CPU/MBoard setups! To me it's a bonus that i'll take & forgive it's inherent hacked design faults.. after all how could i run a system at 1.1gig that was designed to run at 500mhz??
Re: Re: Re: Slot-T vs. modded Slotket one machine over a year, 7x24 until January, the other machine like 7x12 for half a year. Btw, it is not worth fiddling with the voltage clamp as it only decouples 22 signals at most. the cpu busses are always connected directly (data bus 64 bits, address bus 32 bits)
Correcting Tualatin voltages on BX I believe I now understand why Upgradeware and Powerleap do not adapt AGTL+ to AGTL on their Tualatin adapters. If they lowered Vtt to 1.25v on the slotket, they would also have to lower Vref because it needs to be 2/3 Vtt so the CPU can tell a 0 from a 1 reliably. The processor would then see proper AGTL-level inputs, but it would also generate AGTL-level outputs. The BX chipset is still expecting AGTL+ levels, so it probably won't work. The solution is a compromise. Minimum Vtt for AGTL+ is 1.365v, while maximum Vtt for AGTL is 1.3625v - very close to the same voltage. I modded Vtt on my P2B-DS testbed - goal was to change it from 1.535v to 1.365v, but due to resistor tolerances I ended up with 1.372v The board performs exactly as it did before the mod - perfect at 140Mhz, still getting a few memtest errors at 150Mhz, but now the Tualatin processors are running *much* closer to AGTL specs.
Interesting. Obviously such a mod is very board specific. Have you put any details up on your web space? How does Vref measure?
Yes, you'd have to probe the circuit and identify and recalculate the resistors for any board you wanted to do this on - I looked at doing it on my P2B-S boards but haven't proceeded as yet as there are a several large capacitors in the area, making it difficult to access the resistors with a soldering iron - I need a tip with a bit more reach. I measured Vref at 917mV - 2/3 Vtt as expected. The mod was quick and dirty - I just soldered several SMT resistors together to make up the required value because that's all I had. I need to go buy resistors and re-do it neatly. I'll also add a jumper to enable/disable the mod, and at that point I'll take photos and update the web site - I need to add info on the Vio mod as well.
Hmm, I don't think the technical analysis on your page is correct, but congratulations to a running system anyway.
I did not attempt a complete description of the changes Intel made on the Tualatin (for example, I omitted any mention of the new DYN_OE signal), but AFAIK what I posted is technically correct as far as it goes. If you disagree, please elaborate so I can fix it.
Well, this is not the right medium for a document review, nor is it my intention to pick an argument. But since you're asking, let me sketch a few objections. VTT_PWRGD: generated by the mobo, purpose is to latch the VID signals into the VRM. Why intel decided to route it to the FCPGA2 socket is not clear, but certainly not to "tell the cpu to drive the VID signals". TVC16222A: whatever it does, the purpose on certain FCPGA sockets is not to "protect the cpu from excess voltages" because the bus voltages are identical from p2 up to coppermine. Moreover, by lowering the TVC pullup voltage to 1.25, the tualatin cpu would not be "within spec for the most part". There is a control bus with 30 odd signals, data bus with 64 signals, address bus with 32 signals. The TVC can translate 22 or 21 signals. I am also not sure about the "compromise" theory. Assuming there is only one Vtt voltage regulator on the board, which is the source of Vtt and Vref for the whole board, including chipset, socket an cpu, why should one compromise? Just lower it to 1.25V. The other option (and this is the option taken by the BX-mod, by Powerleap and by Socket-T) is to leave Vtt at 1.5V. It seems not to hurt. The cpu seems to accept any combination of Vtt and Vref, as long as board and chipset use the same voltages. OK, no hard feelings. Now prove me wrong.
I prefer to consider it a technical discussion as opposed to a document review - in fact on second thought I might have been better to post here for discussion prior to posting my page Quotes from the PIII-S Datasheet "The VTT_PWRGD signal informs the platform that the VID and BSEL signals are stable and should be sampled. The assertion of the VTT_PWRGD signal indicates the VID signals are stable and are driven to the final state by the processor" and "The DYN_OE allows the BSEL and VID signals to be driven out from the processor. When this signal is low (a condition that will occur if the processor is installed in a non-supported platform), the VID and BSEL signals will be tri-stated and the platform pull-up resistors will set the VID and BSEL to all '1's which is a safe setting" I agree my wording is poor - it does not correctly describe the relationship between VTT_PWRGD and VID signals - but clearly the relationship exists. Actually the CMOS signal groups are specified as 2.5v on Slot 1 processors and 1.5v on S370 processors. These signals are routed through the TVC16222A precisely to protect the CPU from 2.5v on 1.5v pins. There are a total of 27 AGTL signals on a Tualatin processor - 22 i/o, 4 input, and one output. The data and address bus signals are not AGTL, and their specification did not change between Coppermine and Tualatin. There is indeed a single Vtt source, while Vref is derived from Vtt in at least two places - on the slotket and by the BX chipset. The BX chipset is an AGTL+ device, and minimum Vtt for AGTL+ is specified as 1.365v. I doubt it would work with Vtt at 1.25v, but it might be an interesting experiment. Indeed - the processor and chipset must use the same Vtt, and thus Vref, or they would be likely to mis-interpret each other's logic levels, so the slotket makers and modders do not have the option of lowering Vtt on the slotket only. The absolute maximum overshoot voltage for AGTL is specified at 1.78v, 0.53 volts above nominal Vtt of 1.25v. The corresponding figure for AGTL+ is 2.3v, 0.8v above nominal Vtt of 1.5v. When you run a Tualatin processor on a BX board, you are trusting it to control overshoots to no more than 0.28v above nominal Vtt of 1.5v - or in my case 0.25v above a measured 1.53v. I agree it does seem to work, but surely providing a little more overshoot headroom by lowering Vtt cannot be a bad thing considering it does not appear to negatively affect stability. Not my intent at all - mutual edification is my sole reason for participating in this discussion
I'm wrong on that one, the data and address bus signals are AGTL - I misread the datasheet. You are quite correct - it would take a number of TVCs to adjust all those signal levels.
No worries, actually I like this discussion. Maybe we even find a solution to something that has puzzled me for a while: why Vtt_pwrgd has been routed to the fcpga2 socket. I remember this passage well, it describes the purpose of dyn_oe telling the cpu to drive vid and bsel. According to that passage, vtt_pwrgd has no meaning to the cpu. it tells the vrm to latch in the vid signals. A similar description you find in earlier data sheets (fcpga), only that Vtt_pwrgd has not been routed to the S370 before fcpga2. You are right. I had forgotten about that. Interestingly, the CMOS signals are still mostly specified as 1.5V in fcpga2. In cases where the slotkey simply routes Vtt to the TVC this could present a problem when you are trying to lower Vtt to 1.25V. I agree, it depends on the way Vref is arrived at both on the mobo and the slotkey. Also, from the previous paragraph I am beginning to understand that there may be other dependecies introduced by the hardware layout that could cause 1.25V to fail. totally correct, that was one of the earliest comments by one particular expert on arstechnica when the Tualatin core was first released (I forget the nick). I think he argued that Powerleap would never be able to construct a Tualatin slotkey, unless they ran the cpu bus terminators at 1.5V. He didn't think it was feasible. I didn't quite understand at the time, but today we know he was right with the 1.5V and wrong with the feasibility.
I posted a reply yesterday, but it took forever to register and now it's gone... oh well, lets try again. I reviewed the datasheets again with this question in mind, however it remains a mystery to me. The Universal S370 Design Guide for the 815E chipset specifies circuitry to impose a 20ms delay between power on or reset and assertion of VttPWRGD to allow time for chipset voltages and clocks to stabilise, but makes no mention of any use the processor may make of the signal. I tried my slotkets after removing the 3 pins but before installing the AK4 bridge. The Tualeron (stepping tA1) booted, but the PIII-S (tB1) was dead, so it looks like the later stepping may make use of VttPWRGD. That's exactly what the S370-DL does, so my CMOS signals are also running with reduced voltage - but are still (just) within specification and don't seem to be a problem. Yet another reason lowering Vtt all the way to 1.25v may be a bad idea Intel recommends a 75 ohm/150 ohm resistor divider between Vtt and Vss, so I expect that's how it's done. Powerleap are sending me prototypes of their new 'server grade' slotkets for beta testing - these are supposed to be PIII-S SMP capable out of the box. I'll see if I can get their engineers to comment on the issue in the course of my evaluation... I've updated my web page to reflect what I've learned from this discussion so far. Thanks for your input
My tA1 would also run in the Asus-s370-DL without the AK4 bridge, however it refused to boot in my CUBX board without the bridge. The tB1 I have run with the bridge from the start. It seems the effect doesn't depend on the stepping alone... I bet they get "Paul" to tell you some blurb. I have been watching his promises ever since the PL-Pro/II (socket 8 upgrade). It culminated in him getting me to flash a Gigabyte BIOS into my AOpen board when I had trouble with the PL-iP3/T (tualatin slotkey). Luckily I had a flash card to undo the damage... Anyway, as far as I know the only reason why the PL-iP3/T is not SMP capable is that they forgot to connect the corresponding pins. It can be fixed with two pieces of wire. You're most welcome.
